Document:         WhatCPU.txt
File Group:       Benchmarks & Standards
Creation Date:    28 May 2000
Revision Date:    22 September 2002

Title:            CPU ID and Maximum Speed Test
Keywords:         BENCHMARK PERFORMANCE CPU RELIABILITY TEST
                  MMX, SSE, SSE2, 3DNOW 

Abstract:         The program uses special CPU instructions to
                  identify the type of CPU and to measure speed
                  in MHz. Then it executes add instructions via
                  1, 2, 3 and 4 registers to identify maximum 
                  speeds of integer, floating point and MMX 
                  areas. The sum is checked for a simple aid
                  on reliability. Results can be saved in a log
                  file. Version 2.0 includes tests for SSE, 
                  SSE2 and 3DNow instructions, when available.

Contributor:      Roy_Longbottom@compuserve.com

Location          Compuserve PC Hardware Forum

Also via          http://homepage.virgin.net/roy.longbottom/index.htm


CPU ID and MAXIMUM SPEED TEST (CPUID.EXE)

1. Description

The program uses special CPU instructions identify the type of CPU 
and to measure speed in MHz. Then it executes add instructions via 
1, 2, 3 and 4 registers to identify maximum speeds of integer, 
floating point and MMX areas. The sum is checked for a simple aid 
on reliability. Results can be saved in a log file. Version 2.0 
includes tests for SSE, SSE2 and 3DNow instructions, when 
available. Version 2.0 also includes double precision floating 
point calculations besides single precision. These generally 
produce the same speeds but are provided to compare with results of 
the new instructions.

Performance is measured in terms of Integer Millions of 
Instructions Per Second (Integer MIPS) and Millions of Floating 
Point Operations Per Second (MFLOPS). For MMX instructions, that 
use 64 bit registers, Version 1 showed MMX MIPS. As two 32 bit 
integers are added via one instruction, new results are twice those 
in Version 1, with a different definition. Tests now run are for 
the following. 

               32 bit Integer MIPS
               32 bit Float MFLOPS 
               64 bit Float MFLOPS 
               32 bit MMX Integer MIPS
               32 bit SSE MFLOPS 
               64 bit SSE2 MFLOPS 
               32 bit 3DNow MFLOPS

SSE instructions use 128 bit registers for 4 single precision 
floating point words with SSE2 using them for 2 double precision 
words. 3DNow uses the 64 bit MMX registers with two single 
precision words. The same number of instructions is executed for 
each type of instruction (810 million over 4 tests with different 
number of registers), so SSE2 and 3DNow carry out 1620 million 
additions and SSE 3240 million. These are the values that are 
checked for the simple reliability test.

Note: SSE instructions are available on Intel Pentium III onwards 
and SSE2 came with the Pentium 4. AMD Athlon 4 CPUs also 
incorporated SSE instructions. The program tests for availability 
of the new instructions and Operating System support (SSE/SSE2) and 
uses whichever is available.

No installation is necessary. Before running, all other 
applications should be closed. To run, click on the appropriate EXE 
icon and the program starts executing. The program can also be run 
from a BAT file or command line to run, log the results and exit 
automatically. The log file default name is CPUInfo.txt. In normal 
mode a Save button is provided when a different name can be chosen.

Results should be sent to Roy_Longbottom@compuserve.com and details 
of the system under test should be included. 

See CPUID.cpp and Config.cpp for details.

2. Results Log File

Results are appended to the chosen log file. The results are in the 
following format. Example is Intel P4 1900 MHz with Windows XP.

Note that the instruction count for 32 bit Integer MIPS includes 
loop count and branching instructions, so MIPS can be greater than 
MHz (or 2 times for P4) when 1 register is used.
 
#####################################################################
      CPU ID and Speed Test Version 2.0 Sat Sep 14 17:06:19 2002
 
                 Copyright Roy Longbottom 2000 - 2002

 Windows NT Version 5.1, build 2600, 
 Has SSE OS Support, Has SSE2 OS Support, 
 CPU GenuineIntel, Features Code 3FEBFBFF, Model Code 00000F12, 1900 MHz
 Has MMX, Has SSE, Has SSE2, No 3DNow,

 Speeds adding to     1 Register  2 Registers  3 Registers  4 Registers

 32 bit Integer MIPS     3968         4965         5461         5078
 32 bit Float MFLOPS      378          759         1138         1518
 64 bit Float MFLOPS      379          759         1138         1520
 32 bit MMX Int MIPS     1898         3794         3800         3800
 32 bit SSE MFLOPS       1897         3795         3795         3794
 64 bit SSE2 MFLOPS       949         1897         1897         1896

 32 bit Integer MIPS  810M instructions of r=r+1 correct result
 32 bit Float MFLOPS  810M instructions of r=r+1 correct result
 64 bit Float MFLOPS  810M instructions of r=r+1 correct result
 32 bit MMX Int MIPS  810M instructions of r=r+1 correct result
 32 bit SSE MFLOPS    810M instructions of r=r+1 correct result
 64 bit SSE2 MFLOPS   810M instructions of r=r+1 correct result


3. Command Line Parameters

The program can be run from a BAT file or command line with the 
following parameters;

    Auto         Run, log results and exit
    Log aaaaa    where aaaa is the log file name (optional)

    Example      CPUID Auto, Log CPUID4.txt


4. Technical

The program was compiled with Microsoft Visual C++ 6.0 Pro with 
Service Pack 5 and Processor Pack, required to use the new 
instructions. These are used via assembly code or intrinsic 
functions. The Processor Pack includes a help file, procpack.chm, 
that describes all the intrinsics. For full details of Intel 
assembly instructions see intel.com:

 IA-32 Intel Architecture Software Developer's Manual Volume 2: 
 Instruction Set Reference.

This program only uses the simpler floating point instructions. 
There are others for SSE, SSE2 and 3DNow and non-floating point 
instructions. 

SSE and SSE2 use 128 bit registers in Single Instruction Multiple 
Data SIMD mode. SSE is via 4 single precision 32 bit numbers and 
SSE2 via 2 double precision 64 bit numbers. 3DNow uses two 32 bit 
numbers in MMX registers. SSE instructions also need Operating 
System support to control their use, so OS support has also to be 
determined.

Intrinsics can be used directly in the C code e.g. four word 
floating point add:

t0 = _mm_add_ps(t0, t1); where t0 and t1 are 128 bit (__m128)
                         variables.

For the fastest SSE instructions used, all data loaded or stored 
MUST be aligned on 16 byte address boundaries, otherwise the 
program hangs. This is arranged via as series of (example):

 ssum1 = (float *)_aligned_malloc(64, 16);

See CPUID.cpp and Config.cpp for details.
